Audinate releases Dante IP Core
- Details
Development teams can save time, reduce BOM costs and minimize their internal footprint by using a single FPGA to implement both product applications and Dante audio networking, says Audinate. Dante IP Core efficiently runs alongside OEM product applications such as ASRC, audio encryption, and signal processing on a range of Xilinx FPGAs, providing channel counts up to 512x512 with ultra-low latency and sub-microsecond synchronisation.
Dante IP Core reduces the marginal costs of incorporating Dante in FPGA-based products, offering OEMs greater flexibility in aligning product families. Dante IP Core runs on the widely used Xilinx family of FPGAs. and provides all the interfaces required to be a fully functional Dante endpoint, including SiLabs clock synthesis, serial and parallel audio, DDR2 and SRAM, and a variety of standard control interfaces including UART, SPI and I2C.
“Dante IP Core gives savvy manufacturers something they’ve been requesting for a long time.,” says Chris Ware, senior VP of engineering at Audinate. “By integrating Dante IP into FPGA based product designs, they can save costs, reduce board space, and more easily manage thermal constraints while adding features their customers demand.”
Audinate is now a member of the Xilinx Alliance Programme, a global community of qualified vendors that offers IP cores, tools and support for system designers who are developing innovative products using Xilinx FPGAs.
Dante IP Core is available for the Xilinx Spartan 6 family of FPGAs. Support for the Artix 7 FPGA is expected Q1 2018.
(Jim Evans)
